The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) devices. More particularly, the present invention relates to a high voltage transistor protection technique and switching circuit of especial applicability to integrated circuit devices utilizing multiple power supply voltages.
In certain integrated circuit devices (e.g. some memory ICs) a high voltage supply level (xe2x80x9cVPPxe2x80x9d) may be required for proper device operation. When VPP is less than to equal to twice the supply voltage (xe2x80x9cVCCxe2x80x9d), i.e. VPPxe2x89xa62*VCC, then in certain technologies, a single protect transistor may be utilized in a switching circuit wherein the output must be switched between VPP and circuit ground (xe2x80x9cGNDxe2x80x9d or xe2x80x9cVSSxe2x80x9d). The resultant structure is a series connected pair of relatively thin gate oxide MOS transistors coupled between the output node and VSS with the gate of the upper device coupled to VCC and the gate of the lower device defining an input node receiving a switched source of VCC.
In those applications wherein the high voltage supply level is more than twice the device supply voltage (xe2x80x9cVCCxe2x80x9d) i.e. VPP greater than 2*VCC, then a switching circuit comprising a relatively thick gate oxide MOS transistor in series with a pair of series connected relatively thin gate oxide MOS transistors may be coupled between the output node and VSS with the gate of the thick gate oxide device coupled to a source of VPP, the gate of the intermediate N-channel device coupled to VCC and the gate of the remaining N-channel device coupled to an input node receiving a switched source of VCC.
In general, prior art switching circuits for use in devices requiring multiple voltage supply levels, particularly those wherein VPP greater than 2*VCC, have required many transistors in series to convert voltage levels. This results in the consumption of a relatively large amount of on-chip die area for the layout of these circuits along with concomitant device speed degradation.
The high voltage transistor protection technique, of the present invention overcomes the problems inherent in the amount of on-chip die area consumed an d speed degradation of prior art circuit implementations and is of particular applicability to integrated circuit devices employing multiple power supply voltages.
Particularly disclosed herein is a switching circuit for operation in conjunction with a first supply voltage VPP and a second lower supply voltage VCC wherein VPP greater than 2*VCC. The circuit comprises a first transistor having an input terminal thereof coupled between an output of the circuit and an intermediate node with the output capable of transitioning between VPP and a reference voltage level. A second transistor having a switching input thereof is coupled between the intermediate node and a reference voltage line. A substantially direct current voltage source is coupled to the input terminal of the first transistor for supplying a voltage VHVP less than or substantially equal to a maximum gate-to-source voltage VGSMAX of the first transistor. In a preferred embodiment, the voltage VHVP is also less than or substantially equal to a maximum drain-to-source voltage VDSMAX of the second transistor plus a threshold voltage Vt of the first transistor.
Further provided herein is a transistor protection method for a switching circuit having an output transitioning between a first supply voltage VPP and a reference voltage level and an input transitioning between a second supply voltage level VCC and the reference voltage level wherein VPP greater than 2*VCC. The method comprises the steps of providing at least two transistors in series between the output and the reference voltage level, providing a substantially direct current voltage VHVP to a gate terminal of a first transistor, wherein VHVP is less than or substantially equal to a maximum gate-to-source voltage VGSMAX of the first transistor and coupling the input to a gate terminal of the second transistor. In accordance with a preferred method, the substantially direct current voltage VHVP is less than or substantially equal to a maximum drain-to-source voltage VDSMAX of the second transistor plus a threshold voltage Vt of the first transistor.